Some examples of typical data transmission systems will be outlined in the below. First, an optical transmission system will be described with reference to FIG. 2. As shown in FIG. 2, in the transmission system using an optical fiber, in transmitters 10 and 19 on transmitting sides, transmission symbols (digital signals), each of which is the information transmission unit, are converted to analog signals by digital-to-analog converters not shown, and the analog signals are supplied to electric-to-optical converters 12 and 17 such as semiconductor lasers (LDs) and are output into optical fibers 14 and 15 from the electric-to-optical converters 12 and 17 as optical signals. The optical signals that propagate through the optical fibers 14 and 15, respectively, are converted to electric signals by optical-to-electric converters 16 and 13 such as photo diodes (PDs) on receiving sides. Receivers 18 and 11 that receive the electric signals from the optical-to-electric converters 16 and 13, respectively, sometimes execute adaptive equalization, thereby obtaining received symbols after having converted the analog signals to the digital signals using analog-to-digital converters (referred to as “AD converters” or “ADCs”) not shown. With this arrangement, characteristics are improved.
FIG. 3 shows an example of a configuration of a transmission system (a full duplex transmission system) using a twisted pair of cables. Referring to FIG. 3, in this transmission system, each of transmitters 20 and 27 on the transmitting sides converts a transmission symbol (a digital signal) to an analog signal by a digital-to-analog converter not shown, and sends out the analog signal to a transmission line 24 via a hybrid circuit 22 or 26 and a transformer 23 or 25, respectively. Receivers 28 and 21 receive signals sent on the transmission line 24 via the transformers 25 and 23 and the hybrid circuits 26 and 22, respectively, and convert the received analog signals to the digital signals using AD converters not shown. Then, the digital signals are subjected to adaptive waveform equalization. Depending on the system, suppression processing (noise cancellation) of noises such as an echo, a near-end crosstalk, and a far-end crosstalk is also executed.
In recent years, in the receivers in FIGS. 2 and 3 in the transmission system, with a higher transmission speed, the higher speed and the higher accuracy of the AD converter have become necessary. The high speed operation of the AD converter means a high conversion rate (sampling frequency). Further, for implementation of the higher accuracy of the AD converter, in addition to improvement in DC characteristics such as a high resolution, an offset, and a linear characteristic, improvement in a dynamic characteristic (AC characteristic) such as reduction in a sampling clock skew, for example, is also required. Then, the resolution of a high-speed AD converter is comparatively coarse, and implementation of the higher speed and the higher accuracy with one AD converter is difficult, thus leading to a rise in the price.
Then, as a design system for implementing AD conversion with the higher speed and high accuracy, an AD conversion device in which a plurality of AD converters are arrayed in parallel and the respective AD converters are operated with an interleaving method using time division (referred to as an “time-interleaved AD conversion device) has been hitherto employed (refer to Patent Document 1, for example). By driving the plurality of AD converters by frequency-divided clocks of multiple phases mutually different to one another in the time-interleaved AD conversion device, the time-interleaved AD conversion device can accommodate the higher speed while suppressing an increase in the conversion rates of the respective AD converters.
FIG. 10 shows an example of a typical configuration of a conventional time-interleaved AD conversion device. Referring to FIG. 10, this time-interleaved AD conversion device 300 includes first through fourth AD converters 311, 312, 313, and 314 to which an analog input terminal is connected in common. The first through fourth AD converters 311, 312, 313, and 314, respectively execute analog-to-digital conversion responsive to four-phase clock signals CLK1, CLK2, CLK3, and CLK4 that have phases equally spaced each other.
The first through fourth AD converters 311, 312, 313, and 314 that receive a time-continuous analog signal sample the analog signal at equal intervals by time division and convert the analog signal to digital signals. That is, from the first through fourth AD converters 311, 312, 313, and 314, sampled value signals, which are the digital signals obtained by converting the input signals (analog signals) at sampling time points 4×k+0, 4×k+1, 4×k+2, and 4×K+3 of discrete times, in which k is an integer equal to or larger than zero, are output, respectively. The first AD converter 311 outputs a digital signal series D0, D4, and D8 in synchronization with the sampling clock signal CLK1. The second AD converter 312 outputs a digital signal series D1, D5, and D9 in synchronization with the sampling clock signal CLK2 (with a phase thereof being lagged behind the CLK1 by 90 degrees). The third AD converter 313 outputs a digital signal series D2, D6, and D10 in synchronization with the sampling clock signal CLK3 (with a phase thereof being lagged behind the CLK2 by 90 degrees). The fourth AD converter 314 outputs a digital signal series D3, D7, and D11 in synchronization with the sampling clock CLK4 (with a phase thereof being lagged behind the CLK3 by 90 degrees). A parallel-to-serial conversion circuit 320 receives in parallel the digital signals D0, D1, D2, and D3 output from the first through fourth AD converters 311, 312, 313, and 314, respectively, and serially outputs a digital signal series D0, D1, D2, and D3, obtained by multiplexing these in a predetermined timing sequence, as output signals. Then, the parallel-to-serial conversion circuit 320 receives in parallel the digital signals D4, D5, D6, and D7 output from the first through fourth AD converters 311, 312, 313, and 314, respectively, and serially outputs a digital signals series D4, D5, D6, and D7 obtained by multiplexing these in a predetermined timing sequence, as output signals.
In the time-interleaved AD conversion device shown in FIG. 10, it is necessary for the phases of the four-phase clocks CLK1, CLK2, CLK3, and CLK4 are spaced apart at accurately equal intervals. That is, when non-uniformity in sampling periods caused by timing deviation and the like (skews) in the four-phase clocks CLK1, CLK2, CLK3 and CLK4 occurs, inconvenience is caused. This will be described with reference to FIG. 11.
FIG. 11 is a diagram for schematically explaining states of characteristic deterioration in AD converters caused by skews of the sampling clock in the time-interleaved AD conversion device constituted from the two AD converters. Referring to FIG. 11, a horizontal axis indicates time, while a vertical axis indicates signal amplitude. Further, referring to FIG. 11, a timing indicated by an ADC1 shows the sampling phase of a first AD converter. An ADC2 indicates the ideal sampling phase of a second AD converter when the sampling phase ADC 1 of the first AD converter is used as a reference. An analog signal in FIG. 11 indicates the waveform of the time-continuous analog signal supplied as the input signal to the two AD converters. Points of intersection of the timings ADC1 and ADC2 and the waveform of the analog signal indicate time discrete sampled values (ideal sampled values) by the first and second AD converters.
Timings indicated by skew arrows (SKEWs) in FIG. 11 show the timings at which the sampling phases at the timings ADC2 have been deviated by the skews (SKEWs) of the sampling clock.
As shown in FIG. 11, the sampling phases at the timings ADC2 are deviated due to the skews (SKEWs). For this reason, a deviation (noise) is generated between a sampled value under the condition in which a skew (SKEW) is present and an ideal sampled value (the point of intersection of the ADC2 and the analog signal). In case a timing skew is indicated by Δt, a magnitude of the noise ΔV is given by [df(t)/dt] Δt (in which f(t) indicates the waveform of the time-continuous analog signal), and the magnitude depends on the magnitude of the skew Δt and also increases at a location where a differentiation coefficient df(T)/dt of f(t), which is the change rate of the signal waveform, is large (or the location with a large slew rate).
Then, in order to cope with such phase and timing variations, traditionally, a correction circuit for executing phase adjustment has been provided in the time-interleaved AD conversion device.
In Patent Document 1, a configuration having an FIR (Finite Impulse Response) filter is disclosed. In this configuration, the FIR filter receives digital signals from a time-interleaved AD conversion device driven by an even number clock and an odd number clock from a frequency divider. The digital signals output from the FIR filter are made to be a timing pulse accurately shifted by a half period of a sampling clock signal supplied to two AD converters, and the one obtained by delaying the output of a first AD converter by an integer times of the period of the sampling clock signal. That is, outputs of the two output terminals of the FIR filter are alternately output by a multiplexer, thereby allowing accurate shifting of the outputs of the AD converters by the half period of the sampling clock signal, for output. However, in the configuration described in this Patent Document 1, filter coefficients of the FIR filter are set in advance.
Further, In Patent Document 2, a configuration having a unit for calculation of timing offsets is disclosed. In this configuration, the unit for calculation of timing offsets receives digital output signals of a plurality of AD converters juxtaposed, derives timing error estimate values from the sum of the squared differences of sampled values to obtain timing offsets. Then, based on the output of the calculation unit, the output of each AD converters is corrected and multiplexed by a compensation and multiplexing unit. Incidentally, in the Patent Document 2, the calculation unit estimates the amount of compensation using a derivative difference arising from the timing offsets. Then, sampling phase correction is carried out using only a multiplication and a subtraction. Accordingly, a phase shift in a strict sense is not carried out.
FIG. 12 is a diagram showing an example of a configuration of a receiver using a time-interleaved AD conversion device that includes a correction circuit. The receiver shown in FIG. 12 is used as the receiver of the transmission system shown in FIG. 2 or 3, for example. Referring to FIG. 12, this receiver includes two AD converters 301 and 302, a correction circuit 303, a parallel-to-serial converter 304, a divide-by-N frequency division multi-phase circuit 307, an adaptive equalizer 305, and a decision unit 306. The analog input terminals of the AD converters 301 and 302 that input a received analog signal are connected in common, and the AD converters 301 and 302 are placed in parallel. The correction circuit 303 inputs digital signals output from the two AD converters 301 and 302. The parallel-to-serial converter 304 receives two outputs from the correction circuit 303, multiplexes them, for output. The divide-by-N frequency division multi-phase circuit 307 frequency divides a reference clock by N and outputs multi-phase clocks. The decision unit 30 carries out decision of data. The divide-by-N frequency division multi-phase circuit 307 is configured to frequency divide the input reference clock by two and supplies two phase sampling clocks of mutually opposite phases to the two AD converters 301 and 302. For simplicity, FIG. 12 shows two juxtaposed AD converters 301 and 302. However, N (being an integer larger than two, for example) AD converters may be of course juxtaposed.
The two AD converters 301 and 302 carry out respective converting operations in response to the sampling phases which are different according to the multi-phase clocks output from the divide-by-N frequency division multi-phase circuit 307 and output the digital signals. The digital signals output from the two AD converters 301 and 302 are supplied to the correction circuit 303 for timing correction. Then, the digital signals are converted to serial data by the parallel-to-serial converter 304 and sequentially supplied to the adaptive equalizer 305.
The adaptive equalizer 305 receives the digital signal from the parallel-to-serial converter 204 and carries out equalization processing. That is, the adaptive equalizer 305 carries out transmission line compensation, and carries out time-domain adaptive equalization processing (compensation for a gain and a phase) on the signal transmitted through the transmission line and then received at the receiver, for example.
The digital signal with a waveform thereof equalized by the adaptive equalizer 305 is supplied to the decision unit 306, where decision of a received symbol (discrimination of the data) is carried out. By comparing the magnitude of the equalized output of the adaptive equalizer 305 with the magnitude of a predetermined decision threshold, level decision is carried out at the decision unit 306. In the case of multi-valued levels, the number of decision thresholds becomes (the number of the multi-valued levels)−1. In the case of an NRZ (Non Return to Zero) code waveform series, level decision in each bit position is generally executed by sampling at the center of the each bit position (decision point).
The decision unit 306 carries out decision (identification) of the received symbol upon receipt of the equalized output of the adaptive equalizer 305. The decision unit also carries out calculation of a decision error necessary for updating the filter coefficients of the adaptive equalizer 305. That is, the decision unit 306 outputs the error between an equalized output zn of the adaptive equalizer 305 and a reference signal rn as a decision error en of rn−zn. Incidentally, as the reference signal rn, a code point at which the distance between a possible symbol value and the equalized output is minimized may be employed. Alternatively, a predetermined known symbol may be employed.
The decision error output from the decision unit 306 is fed back to the adaptive equalizer 305. The adaptive equalizer 305 is constituted from an adaptive filter for sequentially updating the filter coefficients so as to reduce the value of an objective function (such as the square of the decision error), and with such a configuration, control over the adaptive equalization is carried out.
In the correction circuit 303 in FIG. 12, correction described in the Patent Document 1 or 2, for example, is carried out as correction of the characteristics of the AD converters 301 and 302.                [Patent Document 1]        
JP Patent Kokai Publication No. JP-P2002-100988A                [Patent Document 2]        
U.S. Pat. No. 6,522,282 B1                [Nonpatent Document 1]        
Simon Haykin, “Adaptive Filter Theory” translated by Hiroshi Suzuki et al., KAGAKU GIJUTSU SHUPPANSHA, Inc., page 414.